This invention is directed toward an integrated semiconductor chip package and more particularly a package adapted to be stacked.
Currently marketed integrated semiconductor chip packages, such as the plastic encapsulated dual in-line package (DIP) when stacked on a printed circuit board as might be installed in a computer takes an inordinate amount of space and can fail because of high thermal considerations due to the fact that the chip is totally enclosed in a relatively thick plastic package. A reduction in the overall height of the individual packages would permit an increase in memory and lowering of the space requirements for a more powerful computer while simultaneously reducing some of the thermal aspects which have in the past lead to deterioration of such stacked chip packages.
IBM Technical Disclosure Bulletin, Vol. 8, No. 10, March 1966, page 1314, shows a package which uses a multilevel ceramic carrier with conductors therein and a recess on one side accommodating the semiconductor chip which is connected by the conductors in the ceramic layers to the opposite side of the carrier. The carrier side with the recess is provided with a thin metal foil to improve the cooling properties of the circuit. The chip carrier described in the above-mentioned article is complicated to produce and very expensive because of the multilayered ceramic configuration and is particularly unsuitable for use with memory chips. Additionally, connection of the inverted chip is relatively difficult and requires special fixtures.
Also known are plastic molded (DIP) packages such as shown in U.S. Pat. No. 4,862,245, assigned to the same assignee as the present invention. Such (DIP) packages, too, have disadvantages in that the encapsulation they use is relatively thick and thus limits the number that can be conveniently stacked on a memory card.
Therefore, it is desirable to provide packages of minimum thickness and good thermal qualities whose production can be simplified.